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Single-Phase, Synchronous MOSFET Drivers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V DD = 5V, C DH = 3nF, C DL = 3nF, T A = +25°C, unless otherwise noted.)
SWITCHING WAVEFORMS
(PWM = MID TO LOW TO MID)
MAX8791 toc11
5V
SWITCHING WAVEFORMS
(PWM = HIGH TO MID TO HIGH)
MAX8791 toc12
5V
V PWM
V DL
V LX
5V/div
0
5V
5V/div
0
0
10V/div
V PWM
V DL
V LX
5V/div
0
0
5V/div
10V
10V/div
0
15V
V DH
0
10V/div
V DH
10V/div
0
Pin Description
PIN
1
2
3
4
5
6
7
8
—
NAME
BST
PWM
GND
DL
V DD
SKIP
LX
DH
EP
FUNCTION
Boost Flying-Capacitor Connection. Gate-drive power supply for DH high-side gate driver. Connect a 0.1μF or
0.22μF capacitor between BST and LX.
PWM Input Pin. Noninverting DH control input from the controller IC:
Logic high: DH = high (BST), DL = low (PGND).
Midlevel: After the midlevel hold time expires, the controller enters standby mode. DH and DL pulled low.
Logic low: DH = low (LX), DL = high (V DD ) when SKIP = high.
Internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if
this input is left unconnected (not soldered properly) or driven by a high impedance.
Power Ground for the DL Gate Drivers and Analog Ground. Connect exposed pad to GND.
PWM Low-Side Gate-Driver Output. Swings between GND and V DD . DL forced high in shutdown.
Supply Voltage Input for the DL Gate Drivers. Connect to 4.2V to 5.5V supply and bypass to GND with a 1μF
ceramic capacitor.
Pulse-Skipping Mode Pin. Enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is
operating in SKIP mode:
SKIP = V DD PWM mode
SKIP = GND SKIP mode
An internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left
unconnected (not soldered properly) or driven by a high impedance.
Switching Node and Inductor Connection. Low-power supply for the DH high-side gate driver. LX connects to
the skip-mode zero-crossing comparator.
External High-Side nMOSFET Gate-Driver Output. Swings between LX and BST.
Exposed Pad. Connect to ground through multiple vias to reduce the thermal impedance.
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